Low-capacitance bonding pad for semiconductor device

ABSTRACT

A low-capacitance bonding pad for a semiconductor device. A diffusion region is formed in a substrate, and a bonding pad is formed on the substrate and aligned with the diffusion region. The bonding pad is made from a stacked metal layer and a metal layer. The stacked metal layer is made from a plurality of metal layers and a plurality of dielectric layers, and the metal layers and the dielectric layers are stacked alternately. The metal layers stacked in the stacked metal layer are formed with small areas. Each of the metal layers stacked in the stacked metal layer is coupled with the adjacent metal layer by via plugs.

CROSS-REFERENCE TO RELATED APPLICATION

[0001] This application claims the priority benefit of Taiwanapplication serial no. 88104304, filed Mar. 19, 1999, the fulldisclosure of which is incorporated herein by reference.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention relates to a semiconductor device. Moreparticularly, the present invention relates to a bonding pad with lowcapacitance for a semiconductor device.

[0004] 2. Description of the Related Art

[0005] Trends for electrical products are light, short, small, and thin.Usually, the chips manufacturing technology and the packaging technologyare rapidly developed to meet these trends. However, due to a limitationof bonding machines, a size of a bonding pad for a semiconductor deviceis not reduced as well as a line width of a chip is greatly reduced.Because the size of the bonding pad is insufficiently small, an area ofa substrate overlapped by the bonding pad is large. As a result, aparasitic capacitance of the bonding pad remains high. Additionally, apeel-off effect often occurs while forming the bonding wire, so thatbonding reliability is decreased.

[0006]FIG. 1 is a cross-sectional view, schematically illustrating aconventional bonding pad.

[0007] Referring to FIG. 1, a dielectric layer 12 is formed on asubstrate 10, and a metal layer 14 is formed on the dielectric layer 12.A passivation layer 16 having a bonding pad opening 18 is formed on themetal layer 14. A bonding pad wire 19 is formed on the metal layer 14within the bonding pad opening 18. A parasitic capacitance of thebonding pad maybe small if the distance between the substrate 10 and themetal layer 14 is large. But if the bonding pad is only formed by theuppermost metal layer to increase the distance between the substrate 10and the metal layer 14, the peel-off effect, denoted as a region 17,often occurs during formation of the bonding wire 19 and chip packaging.The bonding reliability is therefore reduced due to the peel-off effect.

SUMMARY OF THE INVENTION

[0008] The present invention provides a low-capacitance bonding pad fora semiconductor device so as to avoid a peel-off effect and reduce aparasitic capacitance of the bonding pad.

[0009] To achieve these and other advantages and in accordance with thepurpose of the invention, as embodied and broadly described herein, theinvention provides a low-capacitance bonding pad for a semiconductordevice. A diffusion region is formed in a substrate at a region on whicha bonding pad is to be formed. The bonding pad includes a stacked metallayer and a metal layer, in which the metal layer is on the stackedmetal layer. The stacked metal layer includes several metal layers andseveral dielectric layers, in which the metal layers are isolated by thedielectric layers in between by alternately stacking them up. The metallayers stacked in the stacked metal layer are formed with small areas.Each of the metal layers stacked in the stacked metal layer is coupledwith an adjacent metal layer by a via plug.

[0010] Since the bonding pad includes several metal layers and burieddeeply in the dielectric layer, the peel-off effect is effectivelyavoided. An area of the substrate overlapped by the metal layers stackedin the stacked metal layer is small because the areas of the metallayers stacked in the stacked metal layer are small. As a result, theparasitic capacitance of the bonding pad is also effectively reduced.Moreover, the parasitic capacitance of the bonding pad is furtherreduced due to the diffusion region in the substrate, which serves as anadditional capacitor coupled in series to the capacitor induced by themetal layers. The metal layers in the stacked metal layer can includevarious geometry structures. For example, the metal layer includesseveral metal bars in one layer and crosses to each other in differentlayer in different bar direction so as to form a geometric structure,such as a net structure or any other overlapping structure.

[0011] To achieve these and other advantages and in accordance with thepurpose of the invention, as embodied and broadly described herein, theinvention provides another low-capacitance bonding pad for asemiconductor device. A device is formed under a bonding pad which ismade from a stacked metal layer and an uppermost metal layer. The metallayers stacked in the stacked metal layer are formed with small area andeach area of the metal layer in the stacked metal layer is smaller thanthe uppermost metal layer.

[0012] The device is formed on a substrate. Several metal layers closeto the device serve as signal lines. Several metal layers stacked on themetal layers as signal lines serve as power lines, and other metallayers stacked on the power lines serve as the bonding pad whichconsists of a stacked metal layer and an uppermost metal layer. Themetal layers in the stacked metal layer can include various geometrystructures. For example, the metal layer includes several metal bars inone layer and crosses to each other in different layer in different bardirection so as to form a geometric structure, such as a net structureor any other overlapping structure.

[0013] Because the device is formed between the bonding pad and thesubstrate, an area of the integrated circuits layout is reduced. Thearea of the substrate overlapped by the metal layers stacked in thestacked metal layer is small since areas of the metal layers are small,so that the parasitic capacitance of the bonding pad is reduced. Thepeel-off effect is avoided and the bonding reliability increases becausethe bonding pad includes the stacked metal layers which are burieddeeply in the dielectric layer.

BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The accompanying drawings are included to provide a furtherunderstanding of the invention, and are incorporated in and constitute apart of this specification. The drawings illustrate embodiments of theinvention and, together with the description, serve to explain theprinciples of the invention. In the drawings,

[0015]FIG. 1 is a schematic drawing, illustrating a cross-sectional viewof a conventional bonding pad;

[0016]FIG. 2 is a schematic drawing, illustrating a top view of abonding pad layout according to the invention;

[0017]FIG. 3 is a schematic drawing, illustrating a cross-sectional viewof FIG. 2 taken along a line III-III;

[0018]FIG. 4 is a schematic drawing, illustrating a cross-sectional viewof FIG. 2 taken along a line IV-IV;

[0019]FIG. 5 is a schematic drawing, illustrating a cross-sectional viewof FIG. 2 taken along a line V-V;

[0020]FIG. 6 is a schematic drawing, illustrating a cross-sectional viewof FIG. 2 taken along a line VI-VI;

[0021]FIG. 7 is another schematic drawing, illustrating a top view of abonding pad layout according to the invention;

[0022]FIG. 8 is a schematic drawing, illustrating a cross-sectional viewof FIG. 7 taken along a line VIII-VIII;

[0023]FIG. 9 is another schematic drawing, illustrating a top view of abonding pad layout according to the invention;

[0024]FIG. 10 is a schematic drawing, illustrating a cross-sectionalview of FIG. 9 taken along a line X-X;

[0025]FIG. 11 is another schematic drawing, illustrating a top view of abonding pad layout according to the invention;

[0026]FIG. 12 is a schematic drawing, illustrating a cross-sectionalview of FIG. 11 taken along a line XII-XII;

[0027]FIGS. 13 through 16 are schematic drawings, illustratingcross-sectional views of bonding pad layouts according to the invention;

[0028]FIGS. 17 through 22 are schematic drawings, illustratingcross-sectional views of bonding pad layouts according to the invention;and

[0029]FIG. 23 is a schematic drawing, illustrating a cross-sectionalview of another bonding pad layout according to the invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0030] Reference will now be made in detail to the present preferredembodiments of the invention, examples of which are illustrated in theaccompanying drawings. Wherever possible, the same reference numbers areused in the drawings and the description to refer to the same or likeparts.

EXAMPLE 1

[0031]FIG. 2 is a schematic drawing, illustrating a top view of abonding pad layout according to the invention. FIGS. 3, 4, 5 and 6 areschematic drawings, illustrating cross-sectional views of FIG. 2 takenalong lines III-III, IV-IV, V-V and VI-VI, respectively.

[0032] Referring to FIGS. 2 and 4, a p-type substrate 200 having ann-well 202 is provided. A p-type doped region 204 is formed as adiffusion region in the n-well 202. A bonding pad includes a stackedmetal layer 208 and a metal layer 250 lies located on the p-typesubstrate 200 and is aligned with the p-type doped region 204. Thestacked metal layer 208 includes several metal layers 210, 220, 230, 240and several dielectric layers 212, 222, 232, 242, 252. Additionally, themetal layers 210, 220, 230, 240 and the dielectric layers 212, 222, 232,242, 252 are stacked alternately on the p-type substrate 200. The metallayer 250 is formed on the dielectric layer 252. In this structure asdescribed above, a junction capacitance C_(p) occurs between the n-well202 and the p-type doped region 204. A junction capacitance C_(N) occursbetween the n-well 202 and the p-type substrate 200. A total equivalentcapacitance C_(Meq) also occurs due to contribution from the metallayers 210, 220, 230, 240, 250. All the capacitance of C_(p), C_(N), andC_(Meq) are coupled in series so that a parasitic capacitance of thebonding pad is effectively reduced.

[0033] The metal layers 210, 220, 230, and 240 are all designed, forexample, to have a bar structures in this embodiment but the metal layer250 is a planar layer. Each width of the metal layers 210, 220, 230 and240 is designed to be as small as possible, so that an area of thep-type substrate 200 overlapped by the metal layers 210, 220, 230 and240 is reduced. This is significantly helpful to reduce the parasiticcapacitance of the bonding pad.

[0034] The metal layers 210 and 240 are parallel to a row direction 400shown in FIG. 2, and the metal layer 240 is aligned with the metal layer210. Additionally, the metal layers 220 and 230 are parallel to a columndirection 300 shown in FIG. 2 and to perpendicular to the row direction400. Similarly, the metal layer 230 is aligned with the metal layer 220.As a result, the metal layers 210 and 240 are shown as a layer structurein FIG. 4 but not shown in FIG. 3 due to the different cross-sectionalline III-III. In FIGS. 5 and 6, the metal layers 210 and 240 are shownlike bars which are not connected to each other, and the metal layer 210is aligned with the metal layer 240. Similarly, the metal layers 220 and230 are shown as bars in FIG. 6 and not shown in FIG. 5. In FIGS. 3 and4, the metal layers 220 and 230 are shown as bars that are not connectedto each other, and the metal layer 230 is aligned with the metal layer220. A layout of the metal layers 210, 220, 230 and 240 resembles a meshor a net as shown in FIG. 2.

[0035] In the invention, each of the metal layers 210, 220, 230, 240 and250 are connected with the adjacent metal layers by via plugs 214, 224,234, 244 in the dielectric layers 222, 232, 242, and 252. In order toavoid the peel-off effect, the via plugs are alternately positioned inthe adjacent dielectric layers 222, 232, 242, and 252 so as to achieve auniform distribution of the via plugs 214, 224, 234, 244. For example,the via plug 244 is not aligned with the via plug 234 as shown in FIG.4. Similarly, the via plug 234 and the via plug 224 are not aligned andthe via plug 224 and the via plug 214 are also not aligned as shown inFIG. 2. This structure can effectively avoid the peel-off effect due toa uniform stress. The via plug 224 connecting the metal layers 220 and230 is only shown in FIGS. 3 and 6. The via plug 214 connecting themetal layers 210 and 220 and the via plug 234 connecting the metallayers 230 and 240 are only shown in FIGS. 4 and 6 due to differentcross-sectional views. The via plug 244 connecting the metal layers 240and 250 is only shown in FIGS. 4 and 5. Furthermore, the via plug 214 isaligned with the via plug 234 and is not aligned with the via plugs 224and 244, as shown in FIGS. 4 and 6.

[0036] A passivation layer 262 is formed on the metal layer 250 with abonding pad opening 270 used for a subsequent bonding process.

[0037] The bonding pad according to the invention includes the stackedmetal layer 208 and the metal layer 250. The peel-off effect iseffectively avoided by this structure. The area of the p-type substrate200 overlapped by the metal layers 210, 220, 230 and 240 is decreased byabout 50% comparing with the conventional bonding pad. Because of thediffusion region, that is, the p-type doped region 204 in the invention,the junction capacitance C_(p) between the n-well 202 and the p-typedoped region 204, the junction capacitance C_(N) between the n-well 202and the p-type substrate 200 and the total equivalent capacitanceC_(Meq) between the substrate 200 and the metal layers 210, 220, 230,240, 250 are series connected. As a result, the parasitic capacitance ofthe bonding pad is about 50% less than that of the conventional bondingpad.

[0038] A layout of the metal layers 210, 220, 230 and 240 mentionedabove is not the only way to reduce the area of the p-type substrate 200overlapped by the metal layers 210, 220, 230 and 240 according to theinvention.

[0039]FIG. 7 is a top view of a portion of a substrate, schematicallyillustrating a bonding pad layout according to the invention, and FIG. 8is a cross-sectional view, schematically illustrating the bonding padtaken along a line VIII-VIII of FIG. 7. In FIGS. 7 and 8, the metallayers are referred in numerals 710, 720, 730, 740 and 750. Each of themetal layers 710, 720, 730 and 740 are designed as a bar, and the metallayer 750 is a planar layer. The metal layers 710, 720, 730 and 740 arealigned with each other and are isolated by several dielectric layers212, 222, 232, 242 in between. A top dielectric layer 252 covers themetal layer 740. The metal layer 750 is located on the dielectric layer252. Additionally, a direction of the metal layers 710, 720, 730 and 740deviates from the direction 400 (FIG. 2) with an angle, which preferablyis 45 degrees in this embodiment.

[0040] Referring to FIGS. 7 and 8, each of the metal layers 710, 720,730, 740 and 750 are coupled with the adjacent metal layers by via plugs714, 724, 734, 744 in the dielectric layers 212, 222, 232, 242.Positions of the via plugs are not aligned for two adjacent layers. Inthis manner, the via plug 714 and the via plug 724 are not aligned, thevia plug 724 and the via plug 734 are not aligned, and also the via plug734 and the via plug 744 are not aligned. The via plug 714 and the viaplug 734 may be aligned and the via plug 724 and the via plug 744 may bealigned. As a result, the position of the via plug 724 connecting themetal layers 720 and 730 is not superimposed on the position of the viaplug 714 used to connect the metal layers 710 and 720 as shown in FIG.8. The position of the via plug 734 connecting the metal layers 730 and740 is not superimposed on the position of the via plug 724. However,the via plug 734 is aligned with the via plug 714, and the via plug 744is aligned with the via plug 724.

[0041] Based on a concept of reducing the area of the substrateoverlapped by the metal layers, other layouts of the metal layers arealso suitable for the invention.

[0042]FIGS. 9 and 11 are top views of a portion of a substrate,schematically illustrating another two bonding pad layouts according tothe invention, and FIGS. 10 and 12 are cross-sectional views,schematically illustrating the bonding pad layouts respectively takenalong lines X-X and XII-XII in FIG. 9 and FIG. 10. A layout of the metallayers in FIG. 9 includes, for example, several concentric circles, anda layout of the metal layers in FIG. 11 is concentric polygons, such assquares.

[0043] In FIGS. 9 and 10, the metal layers are referred in numerals 910,920, 930, 940 and 950. Each of the metal layers 910, 920, 930 and 940are designed as concentric circles, and the metal layer 950 is a planarlayer. Referring to FIGS. 9 and 10, the metal layers 910, 920, 930 and940 are aligned with each other, and each of the metal layers 910, 920,930, 940, 950 are coupled by via plugs 914, 924, 934, 944, which areformed in several isolation layers, such as the dielectric layers 212,222, 232, 242, 252 as shown in the previous examples. Again, the viaplugs 914, 924, 934, 944 are alternately distributed for the twoadjacent layers. The design concept of this layout is the same as theprevious designs.

[0044] In FIGS. 11 and 12, the metal layers are referred to by numerals1110, 1120, 1130, 1140 and 1150. The metal layers 1110, 1120, 1130 and1140 are designed as concentric squares, and the metal layer 1150 is aplane. Referring to FIGS. 11 and 12, the metal layers 1110, 1120, 1130and 1140 are aligned with each other, and each of the metal layers 1110,1120, 1130, 1140 and 1150 are coupled with the adjacent metal layers byvia plugs 1114, 1124, 1134 and 1144. The design concept of this layoutis the same as the previous designs.

[0045]FIGS. 13, 14, 15 and 16 are top views of a portion of a substrate,schematically illustrating other bonding pad layouts for the metallayers 210, 220, 230 and 240 according to the invention. Layouts of themetal layers in FIGS. 13, 14, 15 and 16 respectively are concentricpentagons, concentric hexagons, concentric heptagons and concentricoctagons. The design concept of these layouts is the same as theprevious examples. According to the concept, other kinds of polygons arealso acceptable in the invention.

[0046] In FIGS. 17 and 18, the layouts of the metal layers 210, 220, 230and 240 resemble meshes. The layout shown in FIG. 17 is a honeycombedtype mesh, and the layout shown in FIG. 18 is a mesh composed ofadjacent octagonal units arranged in rows. The mesh in the inventioncomprises a mesh composed of a unit shape as seen in FIGS. 17 and 18.However, a mesh composed of various unit shapes is suitable for theinvention. In FIG. 19, the layout of the metal layers 210, 220, 230 and240 is a mesh composed of rows of pentagonal structures connected by aline, with each pentagonal unit connected to the pentagon in the rowabove or below by a line. Each unit shape of the mesh is changed to aheptagon, an octagon and a circle in FIGS. 20, 21 and 22, respectively.Also, other kinds of polygons are acceptable.

[0047] Although only a few layouts for the metal layers are disclosed inthe embodiment. An implementation of the layout is not limited by thedisclosed examples because the concept disclosed in the invention is toreduce the area of the substrate overlapped by the metal layers. By thisconcept, the parasitic capacitance of the bonding pad is reduced and thepeel-off effect is avoided. As a result, any kind of layout that meetsthe concept is suitable for the invention. The bonding pad layout can bedesigned with many types of unit shape that meet the concept, so thatany kind of geometry is suitable for use in the invention.

EXAMPLE 2

[0048] In a conventional semiconductor device, the bonding pad is notformed above an active device region or circuit region because asubsequent bonding wire process could damage the formed device.

[0049] This issue can also be solved by the invention. Since the bondingpad of the invention include a top metal layer 250 of FIG. 4 and thestacked metal layer 208. The bonding pad opening 270 can be adjusted atthe location above the device region. As a result, the availablesubstrate surface can be more efficiently used.

[0050]FIG. 23 is a cross-sectional view, schematically illustrating abonding pad layout with a device, according to the invention. In thisexample 2, devices are formed on the substrate just under the bondingpad.

[0051] Referring to FIG. 23, a device 32, such as a field effecttransistor, is formed on a substrate 30. Metal layers 51, 52, 53, 54, 55and 56 are formed in a dielectric layer 60 over the device 32, in whichthe dielectric layer 60 serves as an isolation and a frame to stack themetal layers 51, 52, 53, 54, 55, 56. The dielectric layer 60 can alsofurther include several sub-layers to hold and isolate the metal layers.A bonding pad includes the metal layers 55 and 56 and is covered by thea passivation layer 80. The passivation layer 80 includes a bonding padopening 82, which exposes a portion of the metal layer 56. The metallayers 51 and 52 near the substrate 30 are used to serve as, forexample, signal lines, and the metal layers 53 and 54 are designed to beplanar layers and used to serve as, for example, power lines. Apassivation layer 80 is formed on a dielectric layer 60, and the bondingpad opening 82 is formed in the passivation layer 80 to expose the metallayer 56. A bonding wire 84 is attached to the metal layer 56 within thebonding pad opening 84. Each pair of the metal layers 51, 52, 53, 54, 55and 56 is isolated by the dielectric layer 60. The metal layers 55, 56are coupled by a via plug 75 and the metal layers 51, 52 are coupled bya via plug 71. The metal layers 52, 53 and 54 serving as signal linesand power lines are also coupled by via plugs (not shown), and the metallayers 54 and 55 are similar. However, these via plugs should not beformed under the bonding pad opening 82. Thus, the metal layers 53, 54can be used to be the buffer layers, and the bonding stress borne on theactive devices can be reduced through these buffer layers.

[0052] In the invention, the device 32, such as a CMOS device, is formedon the substrate 30 or an n-well 34 in the substrate 30. The metal layer56 is a plane, and the metal layer 55 is designed as applying one of thelayouts shown in example 1 for the metal layer 55 so that the parasiticcapacitance and the bonding reliability of the bonding pad areeffectively reduced and increased, respectively.

[0053] According to the foregoing, the advantages of the inventioninclude the following:

[0054] 1. The bonding pad in the invention is formed by multiple metallayers and buried deeply in the dielectric layer, so that the peel-offeffect is avoided and the bonding reliability effectively increases.

[0055] 2. In the invention, the overlapping area of between thesubstrate and the metal layers is greatly reduced. The parasiticcapacitance of the bonding pad is reduced.

[0056] 3. A diffusion region is formed in the substrate so that thecontact capacitance of the diffusion region and the capacitance of thebonding pad are connected in series. The parasitic capacitance of thebonding pad is reduced.

[0057] 4. The invention is compatible with the current conventionalprocesses. Only the layout design of the bonding pad is changed to meetthe requirement of a semiconductor device. Manufactures can achieve thebonding pad structure of the invention without modifying theirfabrication processes.

[0058] 5. The device can be formed under the bonding pad so that thesubstrate surface is more efficiently used for compact circuit layout.

[0059] It will be apparent to those skilled in the art that variousmodifications and variations can be made to the structure of the presentinvention without departing from the scope or spirit of the invention.In view of the foregoing, it is intended that the present inventioncover modifications and variations of this invention provided they fallwithin the scope of the following claims and their equivalents.

What is claimed is:
 1. A low-capacitance bonding pad structure for asemiconductor device, the structure comprising: a substrate; a stackedmetal layer positioned on the substrate, wherein the stacked metal layerfurther comprises a plurality of metal layers and a plurality ofdielectric layers, which are alternately stacked up, and the metallayers are coupled by a plurality of via plugs in the dielectric layers;an uppermost metal layer positioned on the stacked metal layer, whereinan area of each metal layer in the stacked metal layer is smaller thanthat of the uppermost metal layer; and a passivation layer having abonding pad opening positioned on the uppermost metal layer, wherein thebonding pad opening exposes a portion of the uppermost metal layer. 2.The structure of claim 1 , wherein the metal layers in the stacked metallayer are in the shape of bars.
 3. The structure of claim 2 , whereinthe bar direction of each layer of the metal layers is across to eachother for the different metal layers.
 4. The structure of claim 2 ,wherein the metal layers are stacked and aligned with each other.
 5. Thestructure of claim 1 , wherein the metal layers in the stacked metallayer comprises concentric polygons.
 6. The structure of claim 1 ,wherein the metal layers in the stacked metal layer comprises concentriccircles.
 7. The structure of claim 1 , wherein the metal layers in thestacked metal layer comprises a mesh structure.
 8. The structure ofclaim 7 , wherein the metal layers in the stacked metal layer arealigned with each other.
 9. The structure of claim 7 , wherein the meshis composed of a unit geometric shape.
 10. The structure of claim 9 ,wherein the unit shape is a polygon.
 11. The structure of claim 9 ,wherein the unit shape is a circle.
 12. The structure of claim 1 ,wherein the mesh is composed of various unit shapes.
 13. The structureof claim 1 , wherein locations of the via plugs in two adjacent layersof the dielectric layers are shifted with a proper distance.
 14. Asemiconductor structure, the structure comprising: a substrate; abonding pad over the substrate, wherein the bonding pad comprises astacked metal layer and an uppermost metal layer; and a device locatedon the substrate just under the bonding pad.
 15. The structure of claim14 , wherein the stacked metal layer comprises a plurality of metallayers and a plurality of dielectric layers, which are alternatinglystacked up, and the metal layers are coupled by a plurality of via plugsin the dielectric layers.
 16. The structure of claim 14 , wherein anarea of each metal layer in the stacked metal layer is smaller than thatof the uppermost metal layer.
 17. The structure of claim 14 , whereinthe structure further comprises a signal line and a power line betweenthe device and the bonding pad.
 18. The structure of claim 17 , whereinthe stacked metal layer comprises a plurality of metal layers and aplurality of dielectric layers, which are alternatingly stacked up, andthe metal layers are coupled by a plurality of via plugs in thedielectric layers.
 19. The structure of claim 17 , wherein an area ofeach metal layer in the stacked metal layer is smaller than that of theuppermost metal layer.
 20. The structure of claim 14 , wherein thedevice on the substrate just under the bonding pad is an active device.21. The structure of claim 14 , wherein the device on the substrate justunder the bonding pad is a passive device.
 22. A low-capacitance bondingpad structure for a semiconductor device, the structure comprising: asubstrate having a well; a doped region as a diffusion region formed inthe well; and a bonding pad over the substrate and aligned with thedoped region, wherein the bonding pad comprises a stacked metal layerand an uppermost metal layer.
 23. The structure of claim 22 , whereinions doped in the doped region is opposite to those in the well.
 24. Thestructure of claim 22 , wherein the stacked metal layer comprises aplurality of metal layers and a plurality of dielectric layers, whichare alternatingly stacked up, and the metal layers are coupled by aplurality of via plugs in the dielectric layers.
 25. The structure ofclaim 22 , wherein an area of each metal layer in the stacked metallayer is smaller than that of the uppermost metal layer.